Zhaoxin-specific PadLock/GMI instructions

[tremalrik]

Not too long ago, Zhaoxin (Chinese x86 cpu vendor) published some documentation on a handful of PadLock and GMI cryptographic instructions supported by their processors - see https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3202&tag=0&ref=kfzzc&t=b3f041e6f23d9f48 for the PadLock instructions and https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3152&tag=0&ref=kfzzc&t=32531cd65e657254 for the GMI instructions.

The PadLock instructions include all the old VIA PadLock instructions that XED has been supporting for a while (such as e.g. XSTORE and REP MONTMUL), but also a few new Zhaoxin-specific instructions. The new instructions are, as far as I can tell:

• New Zhaoxin-specific PadLock instructions:
  • REP_XRNG2 (F3 0F A7 F8)
  • REP_XSHA384 (F3 0F A6 D8)
  • REP_XSHA512 (F3 0F A6 E0)
  • REP_XMODEXP (F3 0F A6 F8)
  • REP_MONTMUL2 (F3 0F A6 F0)
• Zhaoxin GMI instructions:
  • SM2 (F2 0F A6 C0)
  • SM3 (F3 0F A6 E8)
  • SM4 (F3 0F A7 F0)

Should XED support these new instructions?

[marjevan]

Hi, and thank you for reaching out.

XED already supports the VIA PadLock instructions that were historically part of the VIA ISA. However, the newly published Zhaoxin-specific PadLock and GMI instructions are not currently supported.

At this time, due to resource constraints and prioritization of features aligned with Intel’s product roadmap, the XED project is not able to commit to supporting instruction sets that are not present in Intel products.

In the meantime, we warmly welcome community contributions. If you’re interested in contributing support for these instructions, feel free to submit a pull request. Please note that external contributions require following the contribution guide. We’d be happy to review any submissions for potential inclusion.